Validation of programmable architectures, consisting of processor cores,
coprocessors, and memory subsystems, is one of the major bottlenecks in current
System-on-Chip design methodology. A critical challenge in validation of such
systems is the lack of a golden reference model. As a result, many existing
validation techniques employ a bottom-up approach to design verification, where
the functionality of an existing architecture is, in essence, reverse-engineered
from its implementation. Traditional validation techniques employ different
reference models depending on the abstraction level and verification task,
resulting in potential inconsistencies between multiple reference models.
This book presents a top-down validation methodology that complements the
existing bottom-up approaches. It leverages the system architect 's